This disclosure relates generally to semiconductor devices and, more particularly, to methods for forming semiconductor devices.
As semiconductor devices have become more highly integrated, the size of chips have decreased and the width of the polysilicon gates of the chips have become narrower.
A conventional method of forming a gate of a semiconductor device will now be described with reference to FIG. 1. A gate polysilicon layer is formed on a semiconductor substrate 11. Then, the gate polysilicon layer is selectively removed by an etching process using a photoresist pattern (not shown) to form a gate electrode 14.
A low concentration ion implantation process is performed to form LDD (lightly doped drain) regions 13. A nitride film is formed on top of the entire structure wherein the gate electrode 14 is formed. Then by etching the nitride film, the nitride film on side surfaces of the gate electrode 14 is left as sidewalls 15 of the gate electrode 14.
Impurity ions are implanted into the LDD regions 13 on both sides of the gate electrode 14 to form source/drain regions 12. A material for forming a silicide layer (e.g., metal) is deposited on a top surface of the entire structure and then an annealing process is performed to form a silicide layer 16 on the exposed surfaces.
In the conventional gate forming method as described above, as the size of the chip becomes smaller, the width of the polysilicon gate becomes narrower, and, as the polysilicon gate becomes narrower, the silicide resistance increases.